Overview
This design uses the DDR SDRAM controller
specifically generated by the Xilinx MIG 2.0 tool for the
Spartan 3E Starter Kit. The burst length is set to two and the
DDR data width is 16 which allows 32-bit words to be read
directly at the MIG interface. This makes the example
extremely simple. The top level test module increments a
counter and an address, writes the counter at the
address, reads the written data back and
displays it on the LCD. Every 0.5 second, the address is
incremented in such a way that each write starts at bank 0,
column 0 and only the row is incremented. Eventually the
address will loop back to the first row.
Supporting documentation
UG086
Xilinx Memory Interface Generator (MIG) User
Guide
Using this design
To use this
design, create the MIG files using the MIG 2.0 tool. You can
find it using the Xilinx CORE Generator, under the folder
"Memories & Storage Elements" -> "Memory Interface
Generator" -> "MIG 2.0".
On the second screen of the
wizard, choose "Create Design for Xilinx Reference Boards" and
choose "Spartan 3E Starter Kit". Then accept the license
agreement and generate the files. The files will be generated
for both Verilog and VHDL. Strangely when generating for a
reference board, the tool will only generate the memory
interface with the testbench. The testbench is comprised of a
set of modules that generate read/writes at different
addresses. The testbench files themselves can be used to
figure out how to use the interface, but here we replace the
testbench with a more simple design.
So remove the top
level module and replace it by this one:
main_00. This module
instantiates the MIG 2.0 memory controller top module (which
contains the user interface), the MIG 2.0 infrastructure
module that contains the DCM and two additional modules which
are a module that takes care of doing reads and writes, and a
module that displays 32-bit numbers on the LCD.
Use the
MIG 2.0 generated ucf file and add the appropriate LED and LCD
instances copying them from the generic ucf file provided by
Xilinx.
LED 7 indicates the memory initialization was
successful and the LCD display can be checked to
(superficially) verify correct read/writes to the DDR
SDRAM.
Design files
spartan_mig20.zip