`include "../rtl/vlog_bl2cl25_parameters_0.v" ////////////////////////////////////////////////////////////////////// // Author: lsilvest // // Create Date: 02/03/2008 // // Module Name: memory_wb_to_mig // // Target Devices: Spartan 3E starter kit Rev D // // Tool versions: Tested with ISE WebPack 9.2 // // Description: This module is the top level module for the Opencores // Ethernet core example. It instantiates the Ethernet core, // the host (loopback_controller), the DDR DSRAM memory, // the infrastructure module that sets up the DLL and the // Ethernet cop that provides arbritration for the Wishbone // interfaces. // //////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2008 Authors // // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal // in the Software without restriction, including without limitation the rights // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell // copies of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in // all copies or substantial portions of the Software. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. ///////////////////////////////////////////////////////////////////////////////// module eth_loopback ( input sys_clk, input reset_in_n, // PHY signals: input E_COL, input E_CRS, output E_MDC, inout E_MDIO, input E_RX_CLK, input E_RX_DV, input [4:0] E_RXD, input E_TX_CLK, output E_TX_EN, output [4:0] E_TXD, // DDR SDRAM signals: inout [15:0] cntrl0_ddr_dq, output [12:0] cntrl0_ddr_a, output [1:0] cntrl0_ddr_ba, output cntrl0_ddr_cke, output cntrl0_ddr_cs_n, output cntrl0_ddr_ras_n, output cntrl0_ddr_cas_n, output cntrl0_ddr_we_n, output [1:0] cntrl0_ddr_dm, inout cntrl0_rst_dqs_div, inout [1:0] cntrl0_ddr_dqs, output [0:0] cntrl0_ddr_ck, output [0:0] cntrl0_ddr_ck_n, // LED signals output [7:0] LED ); // WISHBONE MASTER 1: Ethernet DMA wire [31:0] m1_wb_adr_i; wire [31:0] m1_wb_dat_i; wire [3:0] m1_wb_sel_i; wire m1_wb_cyc_i; wire m1_wb_stb_i; wire m1_wb_we_i; wire [31:0] m1_wb_dat_o; wire m1_wb_ack_o; wire m1_wb_err_o; // WISHBONE MASTER 2: Host (Loopback controller) wire [31:0] m2_wb_adr_i; wire [31:0] m2_wb_dat_i; wire [3:0] m2_wb_sel_i; wire m2_wb_cyc_i; wire m2_wb_stb_i; wire m2_wb_we_i; wire [31:0] m2_wb_dat_o; wire m2_wb_ack_o; wire m2_wb_err_o; // WISHBONE slave 1: Ethernet registers and buffer descriptors wire [31:0] s1_wb_dat_i; wire s1_wb_ack_i; wire s1_wb_err_i; wire [31:0] s1_wb_adr_o; wire [31:0] s1_wb_dat_o; wire [3:0] s1_wb_sel_o; wire s1_wb_we_o; wire s1_wb_cyc_o; wire s1_wb_stb_o; // WISHBONE slave 2: Memory wire [31:0] s2_wb_dat_i; wire s2_wb_ack_i; wire s2_wb_err_i; wire [31:0] s2_wb_adr_o; wire [31:0] s2_wb_dat_o; wire [3:0] s2_wb_sel_o; wire s2_wb_we_o; wire s2_wb_cyc_o; wire s2_wb_stb_o; wire ether_mdo; wire ether_mdio_e; // for the user interface to the ddr wire [2:0] command; wire [((`DATA_MASK_WIDTH*2)-1):0] data_mask; wire [((`DATA_WIDTH*2)-1):0] output_data; wire [((`DATA_WIDTH*2)-1):0] ddr_input_data; wire [((`ROW_ADDRESS + `COL_AP_WIDTH + `BANK_ADDRESS)-1):0] input_address; wire cmd_ack; wire auto_ref_req; wire ar_done; wire burst_done; wire data_valid_out; wire init_done; // for the infrastructure: wire wait_200us; wire sys_rst; wire sys_rst90; wire sys_rst180; wire [4:0] delay_sel_val; wire clk0; wire clk90; // tri-state: assign E_MDIO = ether_mdio_e ? ether_mdo : 1'bZ; //assign LED = 8'b0; // instantiate the ethernet module eth_top ethernet ( // WISHBONE common .wb_clk_i(clk0), .wb_rst_i(sys_rst), // WISHBONE slave .wb_dat_i(s1_wb_dat_o), .wb_dat_o(s1_wb_dat_i), .wb_adr_i(s1_wb_adr_o[11:2]), .wb_sel_i(s1_wb_sel_o), .wb_we_i(s1_wb_we_o), .wb_cyc_i(s1_wb_cyc_o), .wb_stb_i(s1_wb_stb_o), .wb_ack_o(s1_wb_ack_i), .wb_err_o(s1_wb_err_i), // WISHBONE master .m_wb_adr_o(m1_wb_adr_i), .m_wb_sel_o(m1_wb_sel_i), .m_wb_we_o(m1_wb_we_i), .m_wb_dat_o(m1_wb_dat_i), .m_wb_dat_i(m1_wb_dat_o), .m_wb_cyc_o(m1_wb_cyc_i), .m_wb_stb_o(m1_wb_stb_i), .m_wb_ack_i(m1_wb_ack_o), .m_wb_err_i(m1_wb_err_o), //TX .mtx_clk_pad_i(E_TX_CLK), .mtxd_pad_o(E_TXD[3:0]), .mtxen_pad_o(E_TX_EN), .mtxerr_pad_o(E_TXD[4]), //RX .mrx_clk_pad_i(E_RX_CLK), .mrxd_pad_i(E_RXD[3:0]), .mrxdv_pad_i(E_RX_DV), .mrxerr_pad_i(E_RXD[4]), .mcoll_pad_i(E_COL), .mcrs_pad_i(E_CRS), // MIIM .mdc_pad_o(E_MDC), .md_pad_i(E_MDIO), .md_pad_o(ether_mdo), .md_padoe_o(ether_mdio_e), .int_o(ether_int) // ,.LED(LED[3:0]) ); // instantiate the memory // (actually a wishbone interface to MIG interface converter): memory_wb_to_mig mem ( // wb interface: .wb_clk_i(clk0), .wb_rst_i(sys_rst), .wb_adr_i(s2_wb_adr_o), .wb_sel_i(s2_wb_sel_o), .wb_we_i(s2_wb_we_o), .wb_cyc_i(s2_wb_cyc_o), .wb_stb_i(s2_wb_stb_o), .wb_ack_o(s2_wb_ack_i), .wb_err_o(s2_wb_err_i), .wb_dat_o(s2_wb_dat_i), .wb_dat_i(s2_wb_dat_o), // MIG interface: // (note that it also provides the system clock) .mig_clk90(clk90), .mig_init_done(init_done), .mig_output_data(output_data), .mig_input_data(ddr_input_data), .mig_input_address(input_address), .mig_command(command), .mig_cmd_ack(cmd_ack), .mig_data_valid(data_valid_out), .mig_burst_done(burst_done), .mig_ar_done(ar_done), .mig_auto_ref_req(auto_ref_req), .mig_wait_200us(wait_200us), .mig_data_mask(data_mask) ); // instantiate the MIG memory controller: vlog_bl2cl25_top_0 top0 ( .auto_ref_req (auto_ref_req), .wait_200us (wait_200us), .rst_dqs_div_in (cntrl0_rst_dqs_div), .rst_dqs_div_out (cntrl0_rst_dqs_div), .user_input_data (ddr_input_data), .user_output_data (output_data), .user_data_valid (data_valid_out), .user_input_address (input_address[((`ROW_ADDRESS + `COL_AP_WIDTH + `BANK_ADDRESS)-1):0]), .user_command_register (command), .user_cmd_ack (cmd_ack), .burst_done (burst_done), .init_val (init_done), .ar_done (ar_done), .ddr_dqs (cntrl0_ddr_dqs), .ddr_dq (cntrl0_ddr_dq), .ddr_cke (cntrl0_ddr_cke), .ddr_cs_n (cntrl0_ddr_cs_n), .ddr_ras_n (cntrl0_ddr_ras_n), .ddr_cas_n (cntrl0_ddr_cas_n), .ddr_we_n (cntrl0_ddr_we_n), .ddr_ba (cntrl0_ddr_ba), .ddr_a (cntrl0_ddr_a), .ddr_dm (cntrl0_ddr_dm), .user_data_mask (data_mask), .ddr_ck (cntrl0_ddr_ck), .ddr_ck_n (cntrl0_ddr_ck_n), .clk_int (clk0), .clk90_int (clk90), .delay_sel_val (delay_sel_val), .sys_rst_val (sys_rst), .sys_rst90_val (sys_rst90), .sys_rst180_val (sys_rst180) ); // instantiate the DCM and the delay vlog_bl2cl25_infrastructure_top infrastructure_top0 ( .sys_clk (sys_clk), .reset_in_n (reset_in_n), .wait_200us_rout (wait_200us), .delay_sel_val1_val (delay_sel_val), .sys_rst_val (sys_rst), .sys_rst90_val (sys_rst90), .clk_int_val (clk0), .clk90_int_val (clk90), .sys_rst180_val (sys_rst180) ); // instantiate the loopback controller loopback_control lbc ( .wb_clk_i(clk0), .wb_rst_i(sys_rst), .m_wb_adr_o(m2_wb_adr_i), .m_wb_sel_o(m2_wb_sel_i), .m_wb_we_o(m2_wb_we_i), .m_wb_dat_i(m2_wb_dat_o), .m_wb_dat_o(m2_wb_dat_i), .m_wb_cyc_o(m2_wb_cyc_i), .m_wb_stb_o(m2_wb_stb_i), .m_wb_ack_i(m2_wb_ack_o), .m_wb_err_i(m2_wb_err_o) ,.LED(LED[7:0]) ); // instantiate the ethcop that interconnects the 4 wb interfaces eth_cop ecop ( // WISHBONE common .wb_clk_i(clk0), .wb_rst_i(sys_rst), // WISHBONE MASTER 1 .m1_wb_adr_i(m1_wb_adr_i), .m1_wb_sel_i(m1_wb_sel_i), .m1_wb_we_i(m1_wb_we_i), .m1_wb_dat_o(m1_wb_dat_o), .m1_wb_dat_i(m1_wb_dat_i), .m1_wb_cyc_i(m1_wb_cyc_i), .m1_wb_stb_i(m1_wb_stb_i), .m1_wb_ack_o(m1_wb_ack_o), .m1_wb_err_o(m1_wb_err_o), // WISHBONE MASTER 2 .m2_wb_adr_i(m2_wb_adr_i), .m2_wb_sel_i(m2_wb_sel_i), .m2_wb_we_i(m2_wb_we_i), .m2_wb_dat_o(m2_wb_dat_o), .m2_wb_dat_i(m2_wb_dat_i), .m2_wb_cyc_i(m2_wb_cyc_i), .m2_wb_stb_i(m2_wb_stb_i), .m2_wb_ack_o(m2_wb_ack_o), .m2_wb_err_o(m2_wb_err_o), // WISHBONE slave 1 .s1_wb_adr_o(s1_wb_adr_o), .s1_wb_sel_o(s1_wb_sel_o), .s1_wb_we_o(s1_wb_we_o), .s1_wb_cyc_o(s1_wb_cyc_o), .s1_wb_stb_o(s1_wb_stb_o), .s1_wb_ack_i(s1_wb_ack_i), .s1_wb_err_i(s1_wb_err_i), .s1_wb_dat_i(s1_wb_dat_i), .s1_wb_dat_o(s1_wb_dat_o), // WISHBONE slave 2 .s2_wb_adr_o(s2_wb_adr_o), .s2_wb_sel_o(s2_wb_sel_o), .s2_wb_we_o(s2_wb_we_o), .s2_wb_cyc_o(s2_wb_cyc_o), .s2_wb_stb_o(s2_wb_stb_o), .s2_wb_ack_i(s2_wb_ack_i), .s2_wb_err_i(s2_wb_err_i), .s2_wb_dat_i(s2_wb_dat_i), .s2_wb_dat_o(s2_wb_dat_o) ); endmodule // eth_loopback