//////////////////////////////////////////////////////////////////////////////////
// Author: lsilvest
// 
// Create Date:    02/02/2008 
//
// Module Name:    main_00
// 
// Target Devices: Spartan 3E starter kit Rev D
//
// Tool versions:  Tested with ISE WebPack 9.2
//
// Description: This module replaces the top MIG-generated module. It instantiate
//              The memory controller, the infrastructure and provides a very
//              simple testbench.
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Authors
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
/////////////////////////////////////////////////////////////////////////////////

`include "../rtl/vlog_bl2cl25_parameters_0.v"
`timescale 1ns/100ps

module main_00
  (
   output [7:0] LED,
   inout [15:0] cntrl0_ddr_dq,
   output [12:0] cntrl0_ddr_a,
   output [1:0] cntrl0_ddr_ba,
   output  cntrl0_ddr_cke,
   output  cntrl0_ddr_cs_n,
   output  cntrl0_ddr_ras_n,
   output  cntrl0_ddr_cas_n,
   output  cntrl0_ddr_we_n,
   output [1:0] cntrl0_ddr_dm,
   inout  cntrl0_rst_dqs_div,
   input  sys_clk,
   input  reset_in_n,
   inout [1:0] cntrl0_ddr_dqs,
   output [0:0] cntrl0_ddr_ck,
   output [0:0] cntrl0_ddr_ck_n,
   // LCD signals
   output LCD_E,
   output LCD_RS,
   output LCD_RW,
   output [3:0] LCD_D
   );

  // for the infrastructure:
  wire       wait_200us;
  wire       sys_rst;
  wire       sys_rst90;
  wire       sys_rst180;
  wire [4:0] delay_sel_val;
  wire       clk0;
  wire       clk90;

  wire [31:0] number;

  // for the user interface to the ddr
  wire [2:0]  command;           // cs, ras, cas
  wire [((`DATA_MASK_WIDTH*2)-1):0] data_mask;
  wire [((`DATA_WIDTH*2)-1):0]      output_data;
  wire [((`DATA_WIDTH*2)-1):0]      ddr_input_data;
  wire [((`ROW_ADDRESS +
          `COL_AP_WIDTH +
          `BANK_ADDRESS)-1):0]      input_address;
  wire                              cmd_ack;     
  wire                              auto_ref_req;
  wire                              ar_done;
  wire                              burst_done;

  wire  cntrl0_data_valid_out;
  wire  cntrl0_init_done;


  reg [((`ROW_ADDRESS +
          `COL_AP_WIDTH +
          `BANK_ADDRESS)-1):0]      pos_counter;      // counter for writing at diff mem locations
  reg [((`DATA_WIDTH*2)-1):0]       mem_value;        // the value we want to write
  
  // for the LCD
  wire                              if_ready;
  reg                               if_write;
  reg [31:0]                        if_data;
  reg [3:0]                         lcd_state;
  reg [31:0]                        cntr;
  
  // read write module:
  reg                               wr_read;
  reg                               wr_doit;
  wire                              wr_done;
  

//  assign leds[7] = cntrl0_init_done;
  assign data_mask = `DATA_MASK_WIDTH*2'd0;


  parameter START_WRITE          = 4'b0000,
              WAIT_DOIT_WRITE    = 4'b0001,
              WAIT_WRITE         = 4'b0010,
              START_READ         = 4'b0011,
              WAIT_DOIT_READ     = 4'b0100,
              WAIT_READ          = 4'b0101,
              LCD_WRITE          = 4'b0110,
              LCD_IF_WRITE_1     = 4'b0111,
              LCD_SET_IF_WRITE_0 = 4'b1000,
              LCD_WAIT           = 4'b1001;


  // we always keep BANK and COLUMN 0 and use each row to store a value
  // the input address is calculated by shifting the counter by this value:
  parameter ROW_SHIFT = 26'd13;   // COLUMN_ADDRESS + BANK_ADDRESS;
  
  initial begin
    mem_value <= 32'h01234567;
    pos_counter <= 26'b0;
    
    // lcd regs:
    if_data <= 32'habba0123;
    lcd_state <= START_WRITE;
    if_write <= 1'b0;
  end


  always@ (posedge clk0) begin
    case (lcd_state)
      START_WRITE:
        if (!auto_ref_req && cntrl0_init_done) begin
          wr_doit <= 1'b1;
          wr_read <= 1'b0;
          lcd_state <= WAIT_DOIT_WRITE;
        end

      WAIT_DOIT_WRITE:          // wait for the doit signal to be taken
        lcd_state <= WAIT_WRITE;

      WAIT_WRITE:
        begin
          wr_doit <= 1'b0;
          if (wr_done)
            lcd_state <= START_READ;
        end

      START_READ:
        if (!auto_ref_req && cntrl0_init_done) begin
          wr_doit <= 1'b1;
          wr_read <= 1'b1;
          lcd_state <= WAIT_DOIT_READ;
        end
      
      WAIT_DOIT_READ:           // wait for the doit signal to be taken
        lcd_state <= WAIT_READ;

      WAIT_READ:
        begin
          wr_doit <= 1'b0;
          if (wr_done) begin    // read has finished
            lcd_state <= LCD_WRITE;
          end
        end
      
      LCD_WRITE:
        if (if_ready) begin
          if_data <= number;
          if_write <= 1'b1;
          lcd_state <= LCD_IF_WRITE_1;
        end
      
      LCD_IF_WRITE_1:            // this state to keep if_write up for 2 cycles
        lcd_state <= LCD_SET_IF_WRITE_0;       
      
      LCD_SET_IF_WRITE_0:        // set if_write 0 and start the counter 
        begin
          if_write <= 1'b0;
          cntr <= 32'b0;
          lcd_state <= LCD_WAIT;
        end
      
      LCD_WAIT:
        begin
          if (cntr < 25000000) // wait for 0.5 seconds
            cntr <= cntr + 32'b1;  
          else begin
            mem_value <= mem_value + 32'b1;
            pos_counter <= pos_counter + 26'b10000000000000;
            lcd_state <= START_WRITE;
          end
        end
    endcase // case (lcd_state)
  end // always@ (posedge CLK_50MHZ)
  

  // instantiate the MIG2.0 DDR SDRAM controller
  vlog_bl2cl25_top_0 top0
    (
     .auto_ref_req          (auto_ref_req),
     .wait_200us            (wait_200us),
     .rst_dqs_div_in        (cntrl0_rst_dqs_div),
     .rst_dqs_div_out       (cntrl0_rst_dqs_div),
     .user_input_data       (ddr_input_data),
     .user_output_data      (output_data),
     .user_data_valid       (cntrl0_data_valid_out),
     .user_input_address    (input_address[((`ROW_ADDRESS + `COL_AP_WIDTH
                                             + `BANK_ADDRESS)-1):0]),
     .user_command_register (command),
     .user_cmd_ack          (cmd_ack),
     .burst_done            (burst_done),
     .init_val              (cntrl0_init_done),
     .ar_done               (ar_done),
     .ddr_dqs               (cntrl0_ddr_dqs),
     .ddr_dq                (cntrl0_ddr_dq),
     .ddr_cke               (cntrl0_ddr_cke),
     .ddr_cs_n              (cntrl0_ddr_cs_n),
     .ddr_ras_n             (cntrl0_ddr_ras_n),
     .ddr_cas_n             (cntrl0_ddr_cas_n),
     .ddr_we_n              (cntrl0_ddr_we_n),
     .ddr_ba                (cntrl0_ddr_ba),
     .ddr_a                 (cntrl0_ddr_a),
     .ddr_dm                (cntrl0_ddr_dm),
     .user_data_mask        (data_mask),
     .ddr_ck                (cntrl0_ddr_ck),
     .ddr_ck_n              (cntrl0_ddr_ck_n),
     .clk_int               (clk0),
     .clk90_int             (clk90),
     .delay_sel_val         (delay_sel_val),
     .sys_rst_val           (sys_rst),
     .sys_rst90_val         (sys_rst90),
     .sys_rst180_val        (sys_rst180)
     );


  // instantiate the DCM and the delay
  vlog_bl2cl25_infrastructure_top infrastructure_top0
    (
     //    .sys_clkb    (sys_clkb), //SPARTAN-3E STARTER KIT
     .sys_clk   (sys_clk),
     .reset_in_n        (reset_in_n),
     .wait_200us_rout    (wait_200us),
     .delay_sel_val1_val (delay_sel_val),
     .sys_rst_val        (sys_rst),
     .sys_rst90_val      (sys_rst90),
     .clk_int_val        (clk0),
     .clk90_int_val      (clk90),
     .sys_rst180_val     (sys_rst180)
     );

  // instantiate the LCD number writing unit:
  // Instantiate the Unit Under Test (UUT)
  lcd_write_number lcd
    (
     .CLK_50MHZ(clk0), 
     .LCD_E(LCD_E), 
     .LCD_RS(LCD_RS), 
     .LCD_RW(LCD_RW), 
     .LCD_D(LCD_D), 
     .if_data(if_data), 
     .if_write(if_write), 
     .if_ready(if_ready)
     );

  // this module does a read or a write to DDR by generating the
  // correct signals for the MIG DDR module
  ddr_read_write rw
    (.clk0(clk0),
     .clk90(clk90),
     .sys_rst(sys_rst),
     .sys_rst90(sys_rst90),
     .sys_rst180(sys_rst180),
     .user_init_done(cntrl0_init_done),
     .user_output_data(output_data),
     .user_input_data(ddr_input_data),
     .user_input_address(input_address),
     .user_command(command),
     .user_cmd_ack(cmd_ack),
     .user_data_valid(cntrl0_data_valid_out),
     .user_burst_done(burst_done),
    
     .wr_input_data(mem_value),
     .wr_address(pos_counter),
     .wr_output_data(number),
     .wr_read(wr_read),
     .wr_doit(wr_doit),
     .wr_done(wr_done),
     .leds(LED)
     );

 
endmodule